Based on a lot of experiment results, a conclusion is drawn: comparing with other factors, the performance of branch handling strategy is the key limits of processor to exploit the instruction level parallelism existed in nonscientific code, cache miss have severe effect on superscalar processor's performance when it runs scientific code. Second, in order to reduce the branch penalty and improve the performance of superscalar processor, a new branch handling strategy—a classification based hierarchical branch handling strategy, CHBHS is proposed. It first expands the traditional processor architecture to support multiple condition code, conditional execution and Mbranch instruction, as a result, compiler can reduce the number of static conditional branch when the code is generated. Then, CHBHS tries to use the best suitable mechanism to deal with different branch base on their different behavior. CHBHS can predict the target address of unconditional branch, subroutine call and conditional branch by buffering their target address in branch target buffer, a newly proposed high efficient return address stack is used to reduce the penalty of subroutine return instruction, a new Counter Register Stack is also proposed to reduce the penalty of loop-closing branch to zero, and dynamic branch predictor is incorporate with branch target buffer to predict the outcome of conditional branch.

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counter type a/d converter：計(jì)數(shù)式類比/數(shù)位轉(zhuǎn)換器

"洗蝕劑","counter etch" | "計(jì)數(shù)式類比/數(shù)位轉(zhuǎn)換器","counter type a/d converter" | "抵銷的重量","counter weight"

counteract counter-attack counter-revolutionary：反

co- 共同 co-exist co-operate co-editor | counter- 反 counteract counter-attack counter-revolutionary | anti- 反(對),防 anti-tank anti-fascist anti-clockwise

counter blow hammer：對擊鍛造 counter lock 止口鑲嵌方式

corner gate 壓邊澆口 | counter blow hammer 對擊鍛造 counter lock 止口鑲嵌方式 | depression 外縮凹孔